VHDL:Programmeringstips
From Robin
(Difference between revisions)
m |
|||
Line 1: | Line 1: | ||
+ | [[Category:Ressurser|{{PAGENAME}}]] | ||
+ | [[Category:Hardware utvikling|{{PAGENAME}}]] | ||
+ | [[Category:Programmering|{{PAGENAME}}]] | ||
+ | [[Category:VHDL|{{PAGENAME}}]] | ||
= VHDL Programmeringstips = | = VHDL Programmeringstips = | ||
Revision as of 23:29, 10 March 2007
Contents |
VHDL Programmeringstips
Hvordan teste om alle bit i en std_logic_vector = '1'
if A = (A'range => '1') then ... else ... end if;
Hvordan sette alle bit i en std_logic_vector like
A <= (others => '1'); A_2D <= (others=>(others => '1')); --hvis todimensjonalt array
Hvordan vente på en verdi som skal være stabil en periode
wait until (CLK='1' and CLK'stable(2 ns));