From Robin

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		+	[[Category:Ressurser|{{PAGENAME}}]]
		+	[[Category:Hardware utvikling|{{PAGENAME}}]]
		+	[[Category:Programmering|{{PAGENAME}}]]
		+	[[Category:VHDL|{{PAGENAME}}]]
	= VHDL Programmeringstips =		= VHDL Programmeringstips =

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Revision as of 23:29, 10 March 2007

Contents 1 VHDL Programmeringstips 1.1 Hvordan teste om alle bit i en std_logic_vector = '1' 1.2 Hvordan sette alle bit i en std_logic_vector like 1.3 Hvordan vente på en verdi som skal være stabil en periode

VHDL Programmeringstips

Hvordan teste om alle bit i en std_logic_vector = '1'

if A = (A'range => '1') then
   ...
else
   ...
end if;

Hvordan sette alle bit i en std_logic_vector like

A <= (others => '1');
 
A_2D <= (others=>(others => '1'));    --hvis todimensjonalt array

Hvordan vente på en verdi som skal være stabil en periode

wait until (CLK='1' and CLK'stable(2 ns));