FPGA tools
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= Academic Xilinx FPGA tools = | = Academic Xilinx FPGA tools = | ||
Python interface to Xilinx/EDK MHS: https://github.com/EPiCS/reconos/tree/master/tools | Python interface to Xilinx/EDK MHS: https://github.com/EPiCS/reconos/tree/master/tools | ||
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Bitstream Intepretation Library (Virtex5): https://github.com/florianbenz/bil | Bitstream Intepretation Library (Virtex5): https://github.com/florianbenz/bil | ||
DeBit: http://code.google.com/p/debit/ | DeBit: http://code.google.com/p/debit/ | ||
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TORC: http://torc-isi.sourceforge.net/ | TORC: http://torc-isi.sourceforge.net/ | ||
ReconOS: http://www.reconos.de | ReconOS: http://www.reconos.de |
Revision as of 11:40, 15 January 2019
Contents |
FPGA tools on Linux
First time initialization
cd nano .bashrc
Append the following lines to the end of the .bashrc file:
# Questa 10.6c export LM_LICENSE_FILE=5370@lisens.ifi.uio.no export PATH=$PATH:/projects/nanus/eda/Mentor/2017_2018/Questa/questasim/bin # Modelsim library export MODELSIM=/projects/robin/CADlib/modelsimCADLIB.ini # Vivado 16.4 64-bit version source /projects/robin/programs/Vivado/2016.4/settings64.sh export PATH=$PATH:/projects/robin/programs/Vivado/2016.4/bin
After you have added the latter and saved the .bashrc file, restart the terminal.
Launch
Launching the applications is done by entering the following commands in the terminal:
Questa with GUI:
vsim
Vivado with GUI:
vivado
Vlog (terminal only):
vlog
Vcom (terminal only):
vcom
FPGA tools on Windows
Vivado 2016.4 is situated on /uio/kant/ifi-project06/robin/programs/vivado it can be accessed from any Windows machine, but it does need to have the LM_LICENSE_FILE environment variable set to 5370@lisens.ifi.uio.no
Vivado, ISE and Questa is currently installed locally on LISP (2428) and Questa is installed on SED (1454) and CHILL (3443). Please notify the engineer in ROBIN if there are issues.
BUG
Due to technical issues, you will receive the following error when creating a new project in Questa on M:/:
# Project file M:/inf3430/my_first_project.mpf is not readable. # Unable to open project.
We are sorry to inform that there are no current solutions to this problem. However, we are working on a solution. You may use;
C:\users\<username>
for storing project files, but be ware that there is no backup and you need to move your files to M:\ before log out of the client.
You may also use X-Win32 to get Linux with GUI on IFIs Windows clients: https://termvakt.uio.no/Fjerninnlogging#Xterm_via_X-Win32
Digilent Adept on Linux
Digilent Adept to program the Atlys board can be obtained from the Digilent website.
Note that some Xilinx scripts require GNU BASH. Ubuntu (and possibly others) come with DASH. Disable DASH by reconfiguring it:
sudo dpkg-reconfigure dash
Note that the tools available on Windows, such as Xilinx ISE/PlanAhead and Modelsim are not supported by drift on Linux.
To enable autocompletion and history in XMD:
rlwrap xmd
License server
Licenses can be checked out from lisens.ifi.uio.no:
export LM_LICENSE_FILE=5370@lisens.ifi.uio.no
On Windows:
setx LM_LICENSE_FILE 5370@lisens.ifi.uio.no
Academic Xilinx FPGA tools
Python interface to Xilinx/EDK MHS: https://github.com/EPiCS/reconos/tree/master/tools
Bitstream Intepretation Library (Virtex5): https://github.com/florianbenz/bil
DeBit: http://code.google.com/p/debit/
TORC: http://torc-isi.sourceforge.net/
ReconOS: http://www.reconos.de