From Robin

The rules noted here are guidelines that will help creating designs that are easy to verify, read and maintain

VHDL

Sequential logic

• Separate registers from combinational logic

By separating registers from combinational logic you will reduce the risk of creating more registers than you planned to do. By keeping combinational logic in processes that are solely combinational, you will get the full benefit of warnings from the toolchain if you accidentally create latches or registers within the code.

Example:

FSM