Best practice, design and code
From Robin
(→Sequential logic) |
(→VHDL) |
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The rules noted here are guidelines that will help creating designs that are easy to verify, read and maintain | The rules noted here are guidelines that will help creating designs that are easy to verify, read and maintain | ||
- | = | + | = RTL code = |
== Sequential logic == | == Sequential logic == | ||
* Separate registers from combinational logic | * Separate registers from combinational logic | ||
By separating registers from combinational logic you will reduce the risk of creating more registers than you planned to do. By keeping combinational logic in processes that are solely combinational, you will get the full benefit of warnings from the toolchain if you accidentally create latches or registers within the code. | By separating registers from combinational logic you will reduce the risk of creating more registers than you planned to do. By keeping combinational logic in processes that are solely combinational, you will get the full benefit of warnings from the toolchain if you accidentally create latches or registers within the code. | ||
+ | * Register reset should be stated where the registers are assigned. | ||
+ | Reset is for clearing registers to have them in a predictable state. Although synchronous reset can be stated as combinational logic, the use of reset is setting registers, not interfering with the combinational code function. This may seem as a slight contradiction to the bullet above, but once you need to make changes to reset | ||
+ | Example: | ||
+ | REGISTERS: process(clk) is | ||
+ | begin | ||
+ | if rising_edge(clk) then | ||
+ | if rst then | ||
+ | r_signal <= '0'; | ||
+ | r_vector <= (others => '0'); | ||
+ | else | ||
+ | r_signal <= next_signal; | ||
+ | r_vector <= next_vector; | ||
+ | end if; | ||
+ | end if; | ||
+ | |||
+ | next_signal <= valid_a and valid_b; | ||
+ | next_vector <= std_logic_vector("0" & unsigned(a) + "0" & unsigned(b)); | ||
+ | end process; | ||
+ | |||
- | |||
== FSM== | == FSM== | ||
+ | |||
+ | == |
Revision as of 10:06, 15 March 2023
The rules noted here are guidelines that will help creating designs that are easy to verify, read and maintain
RTL code
Sequential logic
- Separate registers from combinational logic
By separating registers from combinational logic you will reduce the risk of creating more registers than you planned to do. By keeping combinational logic in processes that are solely combinational, you will get the full benefit of warnings from the toolchain if you accidentally create latches or registers within the code.
- Register reset should be stated where the registers are assigned.
Reset is for clearing registers to have them in a predictable state. Although synchronous reset can be stated as combinational logic, the use of reset is setting registers, not interfering with the combinational code function. This may seem as a slight contradiction to the bullet above, but once you need to make changes to reset
Example: REGISTERS: process(clk) is begin if rising_edge(clk) then if rst then r_signal <= '0'; r_vector <= (others => '0'); else r_signal <= next_signal; r_vector <= next_vector; end if; end if; next_signal <= valid_a and valid_b; next_vector <= std_logic_vector("0" & unsigned(a) + "0" & unsigned(b)); end process;
FSM
==