From Robin

Revision as of 12:07, 19 May 2008

VHDL Programmeringstips

Hvordan teste om alle bit i en std_logic_vector = '1'

if A = (A'range => '1') then
   ...
else
   ...
end if;

Hvordan sette alle bit i en std_logic_vector like

A <= (others => '1');
 
A_2D <= (others=>(others => '1'));    --hvis todimensjonalt array

Hvordan vente på en verdi som skal være stabil en periode

wait until (CLK='1' and CLK'stable(2 ns));

array/vektorer, forskjellen på downto og to

architecture TESTBENCH of TESTETEST is

signal downs  : std_logic_vector(7 downto 0);
signal ups    : std_logic_vector(0 to 7);

begin

STIMULI : process

 begin
  downs <= x"05";
  wait for 5 ns;
  
  ups <= downs;  -- ups = 0x05
  wait for 5 ns;
  
  downs <= x"03";  
  wait for 5 ns;

--ups(ups'range) <= downs(downs'reverse_range); -- ikke lovlig syntax

  ups(4 to 7) <= downs(3 downto 0); -- ups = 0x04
  wait for 5 ns; 
  
  downs <= x"E4";   
  wait for 5 ns;
  
  ups <= "0000" & downs(3 downto 0); -- ups = 0x04
  wait for 5 ns;
  
  downs <= "1111" & ups(4 to 7); -- downs = 0xF4;
  wait;
 
 end process;

end TESTBENCH;