VHDL:Programmeringstips

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(VHDL Programmeringstips)
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  wait until (CLK='1' and CLK'stable(2 ns));
  wait until (CLK='1' and CLK'stable(2 ns));
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== array/vektorer, forskjellen på '''downto''' og '''to''' ==
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testbenkkode:
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STIMULI : process
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  begin
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downs <= x"05";
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wait for 5 ns;
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ups <= downs;  -- ups = 0x05
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wait for 5 ns;
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downs <= x"03"; 
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  wait for 5 ns;
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--ups(ups'range) <= downs(downs'reverse_range); -- ikke lovlig syntax
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ups(4 to 7) <= downs(3 downto 0); -- ups = 0x04
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  wait for 5 ns;
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  downs <= x"E4"; 
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  wait for 5 ns;
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  ups <= "0000" & downs(3 downto 0); -- ups = 0x04
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  wait for 5 ns;
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  downs <= "1111" & ups(4 to 7); -- downs = 0xF4;
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wait;
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  end process;

Revision as of 12:02, 19 May 2008

Contents

VHDL Programmeringstips

Hvordan teste om alle bit i en std_logic_vector = '1'

if A = (A'range => '1') then
   ...
else
   ...
end if;

Hvordan sette alle bit i en std_logic_vector like

A <= (others => '1');
 
A_2D <= (others=>(others => '1'));    --hvis todimensjonalt array


Hvordan vente på en verdi som skal være stabil en periode

wait until (CLK='1' and CLK'stable(2 ns));


array/vektorer, forskjellen på downto og to

testbenkkode:

STIMULI : process

 begin
downs <= x"05";
wait for 5 ns;
ups <= downs;  -- ups = 0x05
wait for 5 ns;
downs <= x"03";  
 wait for 5 ns;
--ups(ups'range) <= downs(downs'reverse_range); -- ikke lovlig syntax

ups(4 to 7) <= downs(3 downto 0); -- ups = 0x04
 wait for 5 ns; 
 downs <= x"E4";   
 wait for 5 ns;
 ups <= "0000" & downs(3 downto 0); -- ups = 0x04
 wait for 5 ns;
 downs <= "1111" & ups(4 to 7); -- downs = 0xF4;
wait;
 end process;
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