Progress for week 2 (2016)

From Robin

(Difference between revisions)
Jump to: navigation, search
(Budget)
m
Line 21: Line 21:
=== Budget ===
=== Budget ===
* Implement map loading and cost calculation in VHDL model
* Implement map loading and cost calculation in VHDL model
 +
* Improve VHDL<->application communication (find bug that sometimes causes paths to disappear)

Revision as of 17:41, 16 January 2016

Contents

Student template (copy this for your entry)

Budget

  • Todo 1
  • Todo 2

Accounting

  • Done 1
  • Done 2

Eirik Sundet

Budget

  • Meet with FFI-supervisors at Thursday for progress report, and planning further work
  • Continue work with feature analysis
  • making graphs and tables

Accounting

Vegard

Budget

  • Implement map loading and cost calculation in VHDL model
  • Improve VHDL<->application communication (find bug that sometimes causes paths to disappear)


Per Nore

Budget

  • om jeg får lisens til rapidminer, fortsette med testing av algoritmer

Accounting

Personal tools
Front page