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Description of master project

FPGA: Partial reconfiguration for an evolvable hardware classification architecture.

Evolvable hardware (EHW) is a method of designing hardware through evolutionary methods. Through rapid evaluation of thousands of candidate solutions on an FPGA, good solutions can be found in a reasonable amount of time. To allow for rapid configuration of the candidate solutions, a "virtual reconfigurable circuit (VRC)" is often designed by implementing all possible functionality in the FPGA. By simply updating some registers which control multiplexers, different functionality can be achieved. The approach avoids going through synthesis tools with associated long processing times, at the expense of implementing all functionality of the circuit in the FPGA resources. This may lead to high FPGA resource usage, and large architectures may not fit in small, inexpensive devices.

We have earlier proposed an FPGA EHW architecture for classification, using a direct VRC approach. We then proposed a way of reconfiguring some of the look-up tables (LUTs) in the FPGA through a special dual shift register/LUT mode. This allowed for reconfiguring some of the functionality of the architecture in a simple way, without having to resort to re-synthesis. However the method only supported 4-input LUTs and on newer FPGA devices only a fraction of the total amount of LUTs have this functionality. The project consists of investigating and implementing a similar scheme using other reconfiguration techniques, in order to support 6-input LUTs and newer devices.


Kyrre Glette


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